// Created by ihdl
module DIVN_CNTR (
	reset, 
	N, 
	DCO_CLK_IN, 
	DCO_CLK);
   input reset;
   input [6:0] N;
   input DCO_CLK_IN;
   output DCO_CLK;

   // Internal wires
   wire N17;
   wire N18;
   wire N19;
   wire N20;
   wire N21;
   wire N22;
   wire N23;
   wire N24;
   wire N25;
   wire N26;
   wire N27;
   wire N28;
   wire N29;
   wire N30;
   wire n8;
   wire n10;
   wire n11;
   wire n12;
   wire n13;
   wire n14;
   wire n15;
   wire n16;
   wire n17;
   wire n18;
   wire n19;
   wire n20;
   wire n21;
   wire n22;
   wire n23;
   wire n24;
   wire n25;
   wire n26;
   wire n27;
   wire n28;
   wire n29;
   wire n30;
   wire n31;
   wire n32;
   wire n33;
   wire n34;
   wire n35;
   wire n36;
   wire n37;
   wire [6:0] count;

   DFFSR count_reg_0_ (.S(1'b1), 
	.R(n8), 
	.Q(count[0]), 
	.D(N24), 
	.CLK(DCO_CLK_IN));
   DFFSR count_reg_1_ (.S(1'b1), 
	.R(n8), 
	.Q(count[1]), 
	.D(N25), 
	.CLK(DCO_CLK_IN));
   DFFSR count_reg_2_ (.S(1'b1), 
	.R(n8), 
	.Q(count[2]), 
	.D(N26), 
	.CLK(DCO_CLK_IN));
   DFFSR count_reg_3_ (.S(1'b1), 
	.R(n8), 
	.Q(count[3]), 
	.D(N27), 
	.CLK(DCO_CLK_IN));
   DFFSR count_reg_4_ (.S(1'b1), 
	.R(n8), 
	.Q(count[4]), 
	.D(N28), 
	.CLK(DCO_CLK_IN));
   DFFSR count_reg_5_ (.S(1'b1), 
	.R(n8), 
	.Q(count[5]), 
	.D(N29), 
	.CLK(DCO_CLK_IN));
   DFFSR count_reg_6_ (.S(1'b1), 
	.R(n8), 
	.Q(count[6]), 
	.D(N30), 
	.CLK(DCO_CLK_IN));
   INVX1 U9 (.Y(n8), 
	.A(reset));
   AND2X1 U11 (.Y(N30), 
	.B(n10), 
	.A(N23));
   AND2X1 U12 (.Y(N29), 
	.B(n10), 
	.A(N22));
   AND2X1 U13 (.Y(N28), 
	.B(n10), 
	.A(N21));
   AND2X1 U14 (.Y(N27), 
	.B(n10), 
	.A(N20));
   AND2X1 U15 (.Y(N26), 
	.B(n10), 
	.A(N19));
   AND2X1 U16 (.Y(N25), 
	.B(n10), 
	.A(N18));
   AND2X1 U17 (.Y(N24), 
	.B(n10), 
	.A(N17));
   OR2X1 U18 (.Y(n10), 
	.B(n12), 
	.A(n11));
   NAND3X1 U19 (.Y(n12), 
	.C(count[6]), 
	.B(count[4]), 
	.A(count[5]));
   NAND3X1 U20 (.Y(n11), 
	.C(n13), 
	.B(count[2]), 
	.A(count[3]));
   AND2X1 U21 (.Y(n13), 
	.B(count[1]), 
	.A(count[0]));
   OAI21X1 U22 (.Y(DCO_CLK), 
	.C(n16), 
	.B(n15), 
	.A(n14));
   NAND3X1 U23 (.Y(n16), 
	.C(n19), 
	.B(n18), 
	.A(n17));
   NOR2X1 U24 (.Y(n19), 
	.B(N[0]), 
	.A(N[3]));
   OAI21X1 U25 (.Y(n18), 
	.C(n21), 
	.B(n20), 
	.A(N[6]));
   NAND3X1 U26 (.Y(n21), 
	.C(n22), 
	.B(count[6]), 
	.A(N[6]));
   NOR2X1 U27 (.Y(n22), 
	.B(N[4]), 
	.A(N[5]));
   AOI22X1 U28 (.Y(n20), 
	.D(N[4]), 
	.C(n24), 
	.B(N[5]), 
	.A(n23));
   NOR2X1 U29 (.Y(n24), 
	.B(n25), 
	.A(N[5]));
   INVX1 U30 (.Y(n25), 
	.A(count[4]));
   AND2X1 U31 (.Y(n23), 
	.B(count[5]), 
	.A(n26));
   NAND2X1 U32 (.Y(n15), 
	.B(n26), 
	.A(n27));
   INVX1 U33 (.Y(n26), 
	.A(N[4]));
   OAI21X1 U34 (.Y(n27), 
	.C(n29), 
	.B(n28), 
	.A(N[3]));
   NAND3X1 U35 (.Y(n29), 
	.C(n30), 
	.B(n17), 
	.A(N[3]));
   AND2X1 U36 (.Y(n30), 
	.B(count[3]), 
	.A(n31));
   AOI22X1 U37 (.Y(n28), 
	.D(n31), 
	.C(n33), 
	.B(N[0]), 
	.A(n32));
   INVX1 U38 (.Y(n31), 
	.A(N[0]));
   OAI21X1 U39 (.Y(n33), 
	.C(n36), 
	.B(n35), 
	.A(n34));
   NAND3X1 U40 (.Y(n36), 
	.C(N[2]), 
	.B(n34), 
	.A(count[2]));
   NAND2X1 U41 (.Y(n35), 
	.B(n37), 
	.A(count[1]));
   INVX1 U42 (.Y(n37), 
	.A(N[2]));
   INVX1 U43 (.Y(n34), 
	.A(N[1]));
   AND2X1 U44 (.Y(n32), 
	.B(n17), 
	.A(count[0]));
   NOR2X1 U45 (.Y(n17), 
	.B(N[2]), 
	.A(N[1]));
   OR2X1 U46 (.Y(n14), 
	.B(N[6]), 
	.A(N[5]));
   DIVN_CNTR_DW01_inc_0 add_39 (.A({ count[6],
		count[5],
		count[4],
		count[3],
		count[2],
		count[1],
		count[0] }), 
	.SUM({ N23,
		N22,
		N21,
		N20,
		N19,
		N18,
		N17 }));
endmodule
